1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, particularly to a semiconductor device having a multilevel interconnect structure with a connecting portion and a method of manufacturing thereof
2. Description of the Background Art
As a semiconductor device such as the LSI is highly integrated, requirements become severer such as enhancement in dimension accuracy of interconnect lines employed in the semiconductor device, assurance of planarity in a multilevel interconnect structure, and process simplification for reduction of the process cost. A proposed approach which has been attracting attention recently is a buried interconnect process (hereinafter referred to as damascene method), as an idea totally opposed to the conventional interconnect formation method according to which an interconnect line is first processed, an interlevel insulating film is then deposited, and thereafter a planarization process is performed. According to the damascene method, a trench is first generated in an insulating film for producing an interconnect line. The trench is filled with metal such as copper as an interconnect line, and a metal film formed in any region except for the trench is removed by chemical-mechanical polishing (hereinafter referred to as CMP) or like method.
Using the damascene method, the high aspect ratio process of aluminum and the high aspect ratio fill-in process of an insulating film that were conventionally required in the interconnect formation process are unnecessary. An advantage accordingly obtained is that the interlevel insulating film can easily be planarized in the multilevel interconnect structure.
"1997 Symposium on VLSI Technology Digest of Technical Papers" pp. 31-32 discloses a dual damascene method. According to the dual damascene method, a trench for generating an interconnect line as described above and a connection hole for connection with another interconnect layer are generated in one etching process. The trench and the connection hole are then filled with a conductor film such as metal in one film-generation process. A conductor film formed in a region other than the trench is removed by the CMP or the like. The dual damascene method provides the reduced number of manufacturing steps of a semiconductor device.
Referring first to FIGS. 21-25, a method of manufacturing a conventional semiconductor device having an interconnect structure generated by the dual damascene method is briefly described based on the document referred to above.
As shown in FIG. 21, a trench for an interconnect line is formed in an oxide film 101 deposited on a semiconductor substrate (not shown), and the trench is filled with metal such as copper to generate a lower-level interconnect line 102 having a width W1. On the first interlevel insulating film 101 and lower-level interconnect line 102, a second interlevel insulating film 103 formed of a silicon oxide film is formed. The film thickness of the second interlevel insulating film 103 is approximately 0.8 .mu.m. An etching stopper layer 104 formed of a silicon nitride film is formed on the second interlevel insulating film 103. An opening 108 for generating a through hole 109 (see FIG. 23) described below is formed in etching stopper layer 104. The film thickness of etching stopper layer 104 is approximately 0.2 .mu.m. A width W2 of opening 108 is made equivalent to the width W1 of lower-level interconnect line 102.
As shown in FIG. 22, a third interlevel insulating film 105 formed of a silicon oxide film is deposited on etching stopper layer 104. The film thickness of the third interlevel insulating film 105 is approximately 0.9 .mu.m.
A resist pattern (not shown) is next formed on the third interlevel insulating film 105. Using the resist pattern as a mask, the third interlevel insulating film 105 is partially removed by anisotropic etching to generate trenches 106a-106d to be filled with second interconnect lines as shown in FIG. 23. The etching for generating trenches 106b-106d is stopped at etching stopper layer 104. However, in the region below trench 106a, etching still proceeds to partially remove the second interlevel insulating film 103 due to the presence of opening 108 in etching stopper layer 104. Accordingly, through hole 109 is formed in the second interlevel insulating film 103. At the bottom of through hole 109, an upper surface of lower-level interconnect line 102 is exposed. In the etching process for generating trenches 106a-106d to be filled with interconnect lines 107a-107d (see FIG. 25), through hole 109 can subsequently be generated. The resist pattern is thereafter removed.
Within trenches 106a-106d and through hole 109, a Ti film and a TiN film (not shown) are formed. As shown in FIG. 24, a metal film 107 such as copper is deposited in trenches 106a-106d and through hole 109 and on the third interlevel insulating films 105a-105c.
Metal film 107 located on the third interlevel insulating films 105a-105c is thereafter removed by the CMP to generate interconnect lines 107a-107d as shown in FIG. 25.
The semiconductor device is thus manufactured conventionally with an interconnect structure produced by the dual damascene method.
Referring to FIG. 21, according to the conventional dual damascene method illustrated in FIGS. 21-25, the width W2 of opening 108 formed in etching stopper layer 104 is defined to be equivalent to or smaller than the width W1 of lower-level interconnect line 102 or the width of interconnect line 107a (see FIG. 25). In some cases, if opening 108 formed in etching stopper layer 104 is displaced horizontally relative to lower-level interconnect line 102 or interconnect line 107a, the plane area of through hole 109 could be smaller than the area originally designed as shown in FIG. 26. When opening 108 of etching stopper layer 104 is thus displaced relative to lower-level interconnect line 102 or interconnect line 107a, through hole 109 could not reach the upper surface of lower-level interconnect line 102, or the area of the upper surface of lower-level interconnect line 102 exposed at the bottom of through hole 109 could be smaller even if through hole 109 reaches the upper surface of interconnect line 102. A problem then arises is that a proper contact resistance between lower-level interconnect line 102 and interconnect line 107a cannot be obtained.
In the conventional device, when opening 108 formed in etching stopper layer 104 is displaced, the shape of through hole 109 in the plan view is a rectangle as shown in FIG. 26, and depending on the distance of displacement of opening 108, the shape of through hole 109 in the plan view varies. FIG. 26 is a plan view of the semiconductor device shown in FIG. 25 with line 900--900 in FIG. 26 corresponding to the cross section of FIG. 25. In the usual anisotropic etching, control of the etching for generating an opening with a rectangular two-dimensional shape is more difficult than the etching for generating an opening having a circular or square two-dimensional shape. Accordingly, the etching for generating through hole 109 shown in FIG. 23 cannot be controlled precisely to cause problems that through hole 109 does not reach lower-level interconnect line 102 and that damage is given to lower-level interconnect line 102 or other components due to overetching.
Referring to FIG. 27, as the plane area of through hole 109 decreases with miniaturization of the semiconductor device, the rate of change in etch rate increases. FIG. 27 is a graph showing a relation between the plane area of the through hole and the etch rate. When through hole 109 having a plane area smaller than the conventional one is formed, the etch rate changes with variation of the plane area of through hole 109, leading to deterioration of control accuracy of etching. Consequently, through hole 109 is improperly made to cause malfunction of the semiconductor device.